1. Field of the Invention
The present invention relates generally to a semiconductor device and a method for fabricating the same. More particularly, this invention relates to a split gate type transistor, a method for fabricating the same, and a non-volatile semiconductor memory device using split gate type transistors (or memory cells).
2. Description of the Related Art
Recently, a great attention is being paid to non-volatile semiconductor memory devices which include an FRAM (Ferro-electric Random Access Memory), EPROM (Erasable and Programmable Read Only Memory) and EEPROM (Electrically Erasable and Programmable Read Only Memory). The EPROM and EEPROM read data as the floating gate electrode retains charges and the control gate electrode detects a change in threshold voltage according to the amount of the charges. The EEPROM includes a flash EEPROM which can collectively erase data in a whole memory cell array or can partially erase data, block by block, from a memory cell array separated into a plurality of blocks.
A plurality of memory cells (or memory cell transistors) of a flash EEPROM are classified to two types: stacked gate type and split gate type. FIG. 1 shows the cross section of a stack gate type memory cell (or transistor). This memory cell has a P-type single crystalline silicon substrate 101 on which an N-type source region 102 and an N-type drain region 103 are formed with a channel region 104 defined between the two regions. A floating gate electrode 106 is formed over the channel region 104 in a silicon oxide film 105. A control gate electrode 108 is formed over the floating gate electrode 106 in a silicon oxide film 107. Those gate electrodes 106 and 108 have the same width and are stacked one on the other in exact alignment. There are a plurality of floating gate electrodes 106 extending in the direction normal to sheet, while the control gate electrode 108 also extends in the direction normal to the sheet to be shared by the individual floating gate electrodes 106. This control gate electrode 108 serves as a word line.
In this flash EEPROM, each stacked gate type memory cell cannot self-select (or self-determine) its own ON/OFF state. At the time of data erasure, therefore, excess charge draining (excess erasure) from the floating gate electrode 106 allows the associated memory cell to keep the ON state irrespective of the voltage (0V) applied to the control gate electrode 108. This prevents data from being read from the memory cells. To prevent this excess erasure, the erasing procedures of the individual memory cells should be controlled by a peripheral circuit or an external circuit connected to the memory device.
International Publication Number WO92/18980 discloses split gate type memory cells (or transistors) which can avoid such a problem of excess erasure without controlling such erasing procedures. FIG. 2 shows the cross section of this type of memory cell. Within a P-type single crystalline silicon substrate 101 are defined an N-type source region 102 and an N-type drain 103 with a channel region 104 therebetween. A floating gate electrode 106 is formed over a portion of the channel region 104 and a portion of the source region 102 with a relatively thin silicon oxide film 105. A control gate electrode 111 includes a first section 113 and a second section 114. The first section 113 is formed over the floating gate electrode 106 in a relatively thick silicon oxide film 112. The second section 114 is formed over a portion of the channel region 104 in the silicon oxide film 105 and is located directly adjacent to the side wall of the silicon oxide film 112. The second section 114 serves as a select gate, which, together with the source region 102 and drain region 103, forms a select transistor 115. In the split gate type memory cell, therefore, a transistor, which is formed by the floating gate 106, the first section 113 and the source and drain regions 102 and 103, is connected in series to the select transistor 115. This select transistor 115 allows each memory cell to self-select the ON/OFF state. In other words, even when charges are excessively drained from the floating gate 106 so that the channel beneath the gate 106 reaches the ON state, it is possible to selectively make the select transistor 115 conductive or non-conductive by controlling the voltage potential at the control gate 111. U.S. Pat. No. 5,029,130 discloses a flash EEPROM in which the source region 102 is used as a drain region and the drain region 103 is used as a source region.
The source and drain regions 102 and 103 are formed by ion implantation of an impurity in the surface of the silicon substrate 101. In this process, the floating gate 106 and control gate 111 are used as an ion implantation mask. Accordingly, the position of the drain region 103 is determined by the location of the select gate 114, and the position of the source region 102 is determined by the location of the floating gate 106. The floating gate 106 and control gate 111 are separately formed by the deposition of an electrode material, lithography and etching. Therefore, the positions of the floating gate 106 and control gate 111 are not self-aligned but are determined by the mask alignment by lithography.
Suppose that an etching mask 121 is formed slightly off the optimal position as shown in FIG. 3A. When etching is performed under this condition, the shapes of the adjoining control gates 111 become different from each other. As shown in FIG. 3B, the drain region 103 is formed by ion implantation of an impurity in the surface of the silicon substrate 101 with the control gates 111 used as a mask. Consequently, the channel length L1 of the select transistor 115 of one of the adjoining memory cells 122 and 123 does not coincide with the channel length L2 of the other select transistor 115. If the select gate 114 is shorter than the first section 113 in the memory cell 122, the channel length L1 of the select transistor 115 becomes short. If the select gate 114 is longer than the first section 113 in the memory A cell 123, on the other hand, the channel length L2 of the select transistor 115 becomes longer. The select transistor 115 having the long channel length L2 increases the resistance of the channel region 104. As a result, the charge implantation in the floating gate 106 takes a longer time, thus impairing the data writing characteristic. The select transistor 115 having the short channel length L1 decreases the resistance of the channel region 104. Consequently, the select transistor 115 is always turned on so that the associated memory cell does not perform a predetermined operation.
To avoid this drawback, it is necessary to previously provide the positional relation between the individual gates 106 and 111 and the individual regions 102 and 103 with some flexibility in consideration of the precision of the mask alignment as well as the precision of the sizes of the gates 106 and 111. The recent semiconductor technology ensures a work precision of approximately 0.05 .mu.m for thin lines that have widths of around 0.5 .mu.m. The mask alignment precision however is as high as approximately 0.1 to 0.2 .mu.m. This precision hinders the miniaturization of split gate type memory cells, making it difficult to ensure higher integration of flash EEPROMs.
Recently, for MOS (Metal Oxide Semiconductor) transistors, MIS (Metal Insulator Semiconductor) transistors, IGFETs (Insulated Gate Field Effect Transistors) and JFETs (Junction Field Effect Transistors), there is the same demand for further miniaturization as in the case of the split gate type memory cells. In manufacturing an MOS transistor, for instance, a film for forming a gate electrode is formed first. Then, a mask is formed on that film to perform etching, thus yielding a gate electrode of the desired shape. To form the gate electrode that has a short width effective for the miniaturization of transistors, the width of the mask corresponding to the gate electrode should be narrowed. It is, however, difficult to accurately form a mask with a narrow width. The controllability and reproducibility of the gate electrodes having narrow widths are poor, which frustrates the further miniaturization of MOS transistors.